并行计算机体系结构

内容简介

David E. Culler & Jaswinder Pal Singh with Anoop Gupta: Parallel Computer Architecture, A Hard ware/Software Approach. Second Edition.Copyright @ 1996 by Morgan Kaufmann Publishers, Inc. Harcourt Asia Pte Ltd under special arrangement with Morgan Kaufmann authorizes China Machine Press to print and exclusively distribute this edition, which is the only authorized complete and unabridged reproduction of the latest American Edition published and priced for sale in China only, not including Hong Kong SAR and Taiwan. Unauthorized export of this edition is a violation of the Copyright Act. Violation of this Law is subjected to Civil and Criminal penalties.

目录

Contents Foreword Preface 1　Introduction 1.1　Why Parallel Architecture 1.2　Convergence of Parallel Architectures 1.3　Fundamental Design Issues 1.4　Concluding Remarks 1.5　Historical Refernces 1.6　Exercises 2　Parallel Programs 2.1　parallel Application Case Studies 2.2　The Parallelization Process 2.3　Paralleliation of an Example Program 2.4Concluding Remarks 2.5　　Exercises 3　Programming for Performance 3.1　Partitioning for Performance 3.2　Data Access and Communication in a Multimemory System 3.3　Orchestration for Performance 3.4　Performance Factors from the Processor's Perspective 3.5　The Parallel Application Case Studies:An In-Depth Look 3.6　Implications for Programming Models 3.7　Concluding Reamarks 3.8　Exercises 4　Workload-Driven evaluation 4.1　Scaling Workloads and Machines 4.2　evaluating a Real Machine 4.3　evaluating an Architectural Idea or Trade-off 4.4　Illustrating Workload Characterization 4.5　Concluding Remarks 4.6　Exercises 5　Shared Memory Multiprocessors 5.1　Cache Coherence 5.2　Memory consistency  5.3　Design Space for Snooping Protocols 5.4　Assessing Protocol Design Trade-offs 5.5　Synchronization 5.6　Implications for Software 5.7　Concluding Remarks 5.8　Exercises 6　Snoop-based Multiprocessor Design 6.1　Correctness Requirements 6.2　base Design :simgle-Level Caches with an Atomic Bus 6.3　Multilevel Cache Hierarchies 6.4　Split-Transaction Bus 6.5　Case Studies :SGI Challenge and Sun Enterprise 6.6　Extending Cache Coherence 6.7　Concluding Remarks 6.8　Exercises 7　Scalable Multiprocessors 7.1　Scalability 7.2　Realizing Programming Models 7.3　Physical DMA 7.4　User-Level Access 7.5　Dedicated Message Processing 7.6　Shared Physical Address Space 7.7　Clusters and Networks of Workstatiomns 7.8　Implications for Parallel Software 7.9　Synchronization 7.10　Concluding Remarks 7.11　Exercises 8　Directory-based Cache Coherence 8.1　Scalable Cache Coherence 8.2　Overview of Directory-based Approaches 8.3　Assessing Directory Protocols and Trade-Offs 8.4　Design Challenges for Directory Protocols 8.5　Memory-based Directory Protocols:The SGI Origin System  8.6　Cache-based Directory Protocols:The